This invention relates to a process for selectively sealing ferroelectric capacitive elements incorporated in semiconductor integrated non-volatile memory cells.
The invention relates, particularly but not exclusively, to a process for fabricating ferroelectric capacitive elements of non-volatile memory cells of the ferroelectric type and stacked configuration, and the description to follow makes reference to this field of application for simplicity""s sake only.
As is well known, electronic semiconductor ferroelectric non-volatile memory devices comprise pluralities of ferroelectric non-volatile memory cells organized into a matrix array. This means that the cells would be laid in rows or wordlines, and columns or bitlines.
Each ferroelectric non-volatile memory cell comprises a MOS transistor and a ferroelectric capacitive element.
Conventional processes for making such memory cells comprise providing an insulating layer over the entire chip surface, after the MOS transistor has been integrated in a semiconductor substrate. The ferroelectric capacitive element is then formed on top of that insulating layer.
The capacitive element is conventionally provided with a metal lower electrode laid onto the insulating layer.
A layer of a ferroelectric material covers the lower electrode, and a metal upper electrode is laid onto the ferroelectric layer.
However, the presence of hydrogen during subsequent steps to the formation of the ferroelectric capacitive element may affect the ferroelectric material layer, causing its chemio-physical properties, and hence its electric characteristics, to deteriorate.
A prior approach to sealing the ferroelectric capacitive element provides for the use of an insulating layer which is impermeable to hydrogen in a selective way, that is, it is impermeable only in those regions which contain the capacitive element. In fact, hydrogen is a requisite if the electric characteristics of MOS transistors are to be stabilized.
While being in many ways an effective one, this prior approach involves a whole series of dedicated process steps.
An embodiment of this invention provides a process for selectively sealing ferroelectric capacitive elements with such features that the ferroelectric layer can be protected without introducing any additional process steps, thereby overcoming the limitations and drawbacks which still beset prior art processes.
The process selectively seals ferroelectric capacitive elements, wherein the dielectric layer and the sealing layer are defined in one process step.
Specifically, the process selectively seals ferroelectric capacitive elements incorporated in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor. The process includes the following steps: forming said at least one MOS transistor on the semiconductor substrate, depositing an insulating layer over the whole surface of the semiconductor, forming a ferroelectric layer between first and second metal electrodes, forming a sealing layer on the second metal electrode, and defining the sealing layer and ferroelectric layer using a photolithographic process.
The features and advantages of the process according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.